Give a traditional multiple-clock-cycle pipeline diagram of the 5 instructions below assuming the 5 stages we have been using in class. Show any hazards and insert nop's to handle them. Assume the processor has no forwarding. add $r1, $r2, $r3 or $r5, $r2, $r4 and $r6, $r1, $r4 sw $r6, 16($r4)