Given a 3-wide in-order processor, draw the optimal pipeline diagram and answer question 6-9, showing for each instruction, what stage of the pipeline it is in for each cycle for the execution of the code sequence below. Assume full bypassing of values from the respective instruction completion stage to the Decode stage. Assume that pipeline X can execute branches and ALU operations, pipeline Y can excute loads, stores, and ALU operations, and pipeline Z can execute loads, stores, and ALU operations. Loads have a latency of two cycles and ALU operations have a latency of one cycle. Branches are resolved in X0 and the machine has no branch delay slots and always predicts the fallthrough path. The machine can fetch three instructions per cycle, decode three instructions per cycle, execute three instructions per cycle, and writeback three instructions per cycle but maintains data dependencies. The operand steering logic can steer any operand to any ALU to enable any instruction to reach any pipeline, but the pipelines have restrictions on what instructions each can execute as described above. Assume that there are noalignment restrictions on instructions which can be simultaneously fetched from the instruction memory. Also, assume that instructions stall in the decode stage if there are structural or data hazards and stalling one pipeline does not inhibit the fetching of future instructions. The figure below shows the pipeline with pipeline stage names underlined.

Which instructions stall due to data hazard?

Which instructions stall due to structural hazard?

Which instructions stall in the fetch stage?

Which instructions stall in the decode stage?

X0, Branch Cond X1 LU PC addr 0 Y1 rdata IR1 Instr Cache Operand Steering LU RF Read addr RF Write rdata 0 Data Cache R2 LU addr rdata Data Cache X0, Branch Cond X1 LU PC addr 0 Y1 rdata IR1 Instr Cache Operand Steering LU RF Read addr RF Write rdata 0 Data Cache R2 LU addr rdata Data Cache