Given the FIR filter VHDL code:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity firfilter is port( clk, reset: in std_logic; start: in std_logic; a_in: in std_logic_vector(31 downto 0); fir_done_tick, ready: out std_logic; r: out std_logic_vector(31 downto 0) ); end firfilter;

architecture arch of firfilter is type state_type is (idle, op); signal state_reg, state_next: state_type; signal a_reg, r_reg, a_next: unsigned(31 downto 0); signal n_reg, n_next: unsigned(4 downto 0); begin

Continure HERE the fir algorithm

end arch;