Given the following Circuit: X D Z K dlock a. The State Table for the above circuit is: Present State Next State Output AB A' B' z X=0 X=1 X=0 X=1 00 01 00 1 0 11 00 1 10 11 00 0 11 11 b. For the logic signal x given below, the following timing trace is correct. X A 0 0 o 0 1 1 1 0 10 0 0 0 1 1 1 0 10 0 0 n Given the following Circuit: X D Z K dlock a. The State Table for the above circuit is: Present State Next State Output AB A' B' z X=0 X=1 X=0 X=1 00 01 00 1 0 11 00 1 10 11 00 0 11 11 b. For the logic signal x given below, the following timing trace is correct. X A 0 0 o 0 1 1 1 0 10 0 0 0 1 1 1 0 10 0 0 n