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Given the following MIPS assembly like code: Li R 8 , 8 L: , L W R 2 , R 3 , R 7 Add

Given the following MIPS assembly like code:
Li R8,8
L: ,LWR2,R3,R7
Add R1, R2, R3
Sub R7, R1, R3
LW R4,10(R7)
SW R4,20(R1)
Subi R8, R8,4
BNEQZ R8, L
Also, given the following latencies for each stage:
IF: 80ns, ID: 30ns, EX: 50ns, MEM: 85ns, and WB: 35ns
What is the average CPI when running this code on Multi-cycle MIPS CPU with the above latencies?
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