Given the following switching functions with four inputs, a, b, c, and d and four outputs, F1, F2, F3 and F4:

F1 (a, b, c, d) = m (3, 4, 6, 9, 11) + d (7, 12)

F2 (a, b, c, d) = m (2, 4, 8, 10, 11, 12) + d (6, 7, 9)

F3 (a, b, c, d) = m (3, 6, 7, 10, 11) + d (4, 9, 12)

F4 (a, b, c, d) = m (2, 6, 10, 11, 12) + d (4)

1. Design the switching functions using minimal number of gates (make sure to use overlapping as much as you can).

2. Design the switching functions using minimal NAND gates only.

3. Design the switching functions using minimal NOR gates only.

4. Design the switching functions using minimal PLA.

5. Design the switching functions using a ROM.

6. Design the switching functions using 4:1 MUXs (the 4:1 MUXs must be designed using the 2:1 MUXs*).

7. Design the switching functions using 8:1 MUXs (the 8:1 MUXs must be designed using the 4:1 MUXs*).

8. Design the switching using 3:8 DMUXs and minimal logic gates (the 3:8 DMUXs must be designed using the 2:4 DMUXs*).