Given the following timing parameters of FIR filter: \( T_{\text {lopic_mult }}=3 n \) s, \( T_{\text {logic_adoer }}= \) 2ns,Tsouting=0ns,Tclk-a=0.2ns,Tsetwp=0.2ns and Tshw=+0.2ns. Where Tskew= SCP delay - DCP delay. i. Calculate the maximum clock frequency and throughput of FIR filter, where ho to h3 are 8-bit constants. Xn is an 8-bit input of FIR filter connected to an input port of FPGA and Yn is the 18-bit output of FIR Filter. ii. Optimize the FIR Filter to operate on a max clock time period of 4 ns. How many pipeline stages will be required for targeting this clock time period? Show the block diagram with pipeline stages. iii. Calculate the maximum clock frequency and throughput of filter in part ii. iv. If the input delay of Xnn is 0.5ns, is there a potential set up time violation in the pipelined eircuit of part ii for Tck=4ns ? Equation for FIR Filter: Yn=h0Xn+h1Xn1+h2Xn2+h3Xn1