Given the following Verilog code, Complete the 4-bit subtractor and any other gates required to implement N, Z, C, and V.

module fa( output logic cout, s, input logic a, b, cin ); assign {cout,s} = a + b + cin; endmodule

module cond_code(output logic n, z, c, v, input logic signed [3:0] a, b ); //complete using the fa module endmodule

Test Bench:

module main; logic tn, tz, tc, tv; logic signed [3:0] ta, tb; logic pass_fail; task check_cc( logic signed [3:0] a, b, logic n, z, c, v ); ta = a; tb = b; #10; $display("testing a=%1d b=%1d n=%b z=%b c=%b v=%b", a, b, tn, tz, tc, tv); if ( tn !== n ) begin $display( "n is %1b should be %1b", tn, n ); pass_fail = 0; end if ( tz !== z ) begin $display( "z is %1b should be %1b", tz, z ); pass_fail = 0; end if ( tc !== c ) begin $display( "c is %1b should be %1b", tc, c ); pass_fail = 0; end if ( tv !== v ) begin $display( "v is %1b should be %1b", tv, v ); pass_fail = 0; end endtask cond_code dut( tn, tz, tc, tv, ta, tb); initial begin pass_fail = 1; check_cc( 7, 7, 0, 1, 1, 0); check_cc( 7, -7, 1, 0, 0, 1); check_cc( -7, 7, 0, 0, 1, 1); check_cc( 1, 2, 1, 0, 0, 0); check_cc( 2, 1, 0, 0, 1, 0); check_cc( 0, 0, 0, 1, 1, 0); check_cc( 4, -4, 1, 0, 0, 1); check_cc( -4, 4, 1, 0, 1, 0); check_cc( 3, -3, 0, 0, 0, 0); check_cc( -3, -3, 0, 1, 1, 0); if ( pass_fail ) $display(" Test passed"); else $display(" Test failed"); $finish; end endmodule