Hello,

I really need some help with the following project.

For this second project, you will proceed with the design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. The flip flops are available in .mf library. This flip flops come in Dual-Packages so all you need is two of them. Implementation with other class of devices, like 71LS161/163 will not be considered. You need to take into consideration the following: a) The simulations should use a clock of 25 MHz b) The snap shots should show a complete count (from 0000 to 1111 and another for a count from 1111 to 0000), and should show uses of Asynchronous Clear and Preset.

Please note: It is imperative that we use the 74112 Flip Flop. I.E: Using Quartus II a block diagram/schematic.