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A MIPS like processor has 256 registers with 2KB register file. This processor supports three types of instructions R,I and J (classification is similar to MIPS) and total of 95 instructions. OpCode for R type instruction is 00 and there are total 32R type instructions. What is minimum number of bits needed to encode this processor's instruction set? 40 None of these 64 41 32 1. Compute number of bits per register. This will determine number of bits needed for 'shamt' field. 2. Number of register should give you number of bits needed for rs, rt, rd fields. 3. Determine number of bits required by 'opcode' and 'funct' from given information about number of instructions. Review following piece of assembly code and construct symbol table starting relative address at 0 (i.e. treat first line as ' 0 ' instead of ' 1 ') 1. MAIN: 2. add r3,r4,r5 3. 4. addi r4,r4,1 5. LOOP: jal MY_PROC 6. addi r5,r5,1 7. L2: 8. bne r4, r5, LOOP 9. L3: j EXIT MAIN LOOP L2 L3 What can be told about 'pseudo instruction' supported by assemblers? They are not implemented on processor All of these Can be written using couple of native instructions None of these Assembler automatically replace those pseudo instructions into combination of native instructions. They are macros An assembly program defined two macros - Macro_A and Macro_B. Macro_A contains 7 instructions of which 2 are call to Macro_B. Macro_B contains 10 instructions. The main assembly program contains 25 instructions of which 2 are calls to Macro_A and 3 are calls to Macro_B. How many machine code will be created for this assembly program