Help please I need

the truth table SOP for each output

Kmaps and min SOP

Verilog code

Problem statement: In this project, you will design and implement a Logic Unit using Quartus II design tools. The system will take two 4-bit data inputs X3..XO and Y3.. YO and 2-bits control signal c1 c2. The output depends on the designing of the problem. Table 1 explains the Logic Units operations in more details. c1 co Operation 0 0 1 F = 5211_Code (X) 0 1 2 F = 2 Y 3 X + 2 y + 3 Table 1: System functionality 10 Operation 1: Design a combinational circuit that takes 4-bits X as input and give the equivalent 4-bit 5211 code as output. 5211 code is a weighted code, its weight are 5, 2, 1 and 1. A decimal number is represented in a 4-bits form and the total four bits weight is 5 + 2 + 1 + 1 = 9 Hence, the 5211 code represents the decimal numbers from 0-9. Assume that the inputs greater than represent illegal codes and can be treated as don't cares. Example: The bit assignment 1011 can be seen by its weight to represent the decimal 7 because: 5*1 + 2*0 + 1*1 + 1*1 = 7 Follow the steps for combinational circuit design and find the minimum SOP for each output. Implement the design using Verilog and verify using waveform