Help with detecting pipeline Hazards

The image below is an example of how it is done

Below is a sequence of RISC-V instructions. The pipeline diagram shows when each instruction will be in each stage of the pipeline. In this diagram, each row represents a cycle and each column represents a different pipeline stage. All instructions go through the IF and ID stages. Integer instructions go through the EX, MEM, and WB stages. Floating-point load instructions go through EX, MEM, and FWB stages. Floating-point add and subtract operations go through the FADD and FWB stages, do not go through MEM stage, and require 4 cycles during execution. Store instructions do not perform a write-back stage. 1. fadd.s f2,fo,fl 2. add 4,5,6 3. flw f1, 4(x2) 4. fsub.s f3,f4,f5 5. or 3,2,6 6. Isw f3, 8(x3) 7. fadd.s f4,f3,f2 8. Iw x1,4(x2) 9. SW x1,8(x2) L0. fsub.s f5,f2,f3 1. fadd.d f4,f0,f2 2. Iw x3,0(x1) 3. add 4,4,3 4. sw x4,0(x1) 5. addi 1,1,8 \begin{tabular}{|c|c|c|c|c|c|c|c|} \hline cycle & IF & ID & EX & MEM & WB & FADD & FWB \\ \hline 1 & 1 & & & & & & \\ \hline 2 & 2 & 1 & & & & & \\ \hline 3 & 3 & 2 & & & & 1 & \\ \hline 4 & 4 & 3 & 2 & & & 1 & \\ \hline 5 & stall & stall & & 2 & & 1 & \\ \hline 6 & 5 & 4 & 3 & & 2 & 1 & \\ \hline 7 & & 5 & 4 & 3 & & & 1 \\ \hline 8 & & & 5 & 4 & 3 & & \\ \hline 9 & & & & 5 & & & \\ \hline 10 & & & & & 5 & & \\ \hline \end{tabular}