Here below is my finished vhdl code for a fir iir filter. please help me create a simple array inside my behavioral code under the process section that inputs a series of 8 bit random input values. my code works and runs perfectly I just need a series in my behavioral code that the filter inputs and outputs in a simulation. the problem is that when i run it with my testbench it doesnt properly input assigned values and doesnt out put he right computation of the input values .Anything helps please below I have attached my behavioral code and test bench code. please help. thank you. show me that it runs pls will like asap .

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

-- declared entity

entity register_8bit is

Port (

-- Clock input

clk : in std_logic;

-- Data input

din : in std_logic_vector (7 downto 0);

-- Data output

dout : inout std_logic_vector (7 downto 0)

);

end register_8bit;

-- Architecture declaration

architecture behavioral of register_8bit is

-- Signal to store the value of the input

signal stored_value : std_logic_vector (7 downto 0);

-- Signal to store the calculated value

signal calculated_value : integer range 0 to 255;

begin

-- Process to update the stored value and calculate the new value on every rising edge of the clock

process (clk)

variable Stored_value_intger : integer;

variable dout_intger : integer;

begin

if (clk'event and clk = '1') then

-- Updated the stored value with the current input

stored_value <= din;

-- Calculation of the new value based on the stored and previous input this failes

Stored_value_intger := to_integer(unsigned(stored_value));

dout_intger :=to_integer(unsigned(dout));

calculated_value <= 2 * Stored_value_intger + dout_intger ;

end if;

end process;

-- Assigning the stored value to the output

dout <= stored_value;

end behavioral;

////////////////////////////////////////////////////////////// test bench below

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity register_8bit_tb is

end register_8bit_tb;

architecture testbench of register_8bit_tb is

-- Component declaration

component register_8bit is

port (

clk : in std_logic;

din : in std_logic_vector (7 downto 0);

dout : inout std_logic_vector (7 downto 0)

);

end component;

-- Signals declaration

signal clk : std_logic := '0';

signal din : std_logic_vector(7 downto 0) := "00000001";

signal dout : std_logic_vector(7 downto 0);

begin

-- the device under test

uut: register_8bit port map (

clk => clk,

din => din,

dout => dout

);

-- Toggle clock signal for 10 cycles

process

begin

for i in 1 to 10 loop

clk <= not clk;

wait for 10 ns; -- adjusting time delay as needed

end loop;

wait;

end process;

end testbench;