Here is a verilog question I can't fix.

The question asked to produce a PWM signal that produces pulses.

The length in pulse length is to be controlled by the user.

Let's assume that we are going produce a system generates two pulses whose lengths are 1.5ms and then produce two pulses whose lengths are 1.8ms,and then reapeating back to the first two pulses(1.5ms).

And the system should have an input that allows you to change whether it is using the (1.5ms 1.8ms) or (1.4ms 1.7ms) values to produce the pulses.

(if we choose the first pair, the first two pulses are 1.5ms and sencond two pulses are 1.8ms.

if we chhose the second pair, he first two pulses are 1.4ms and sencond two pulses are 1.7ms )

Please using the verilog HDL to write and provide ASM or state diagrams.

Thank you.