Here is my verilog code and the testbench code however there is an issue with my waveform not being accurate can you please find the issue and explain why?

module line $($

input wire rst$\_$n$,//$ Active low reset

input wire clk$,//$ Clock

input wire signed $[3$:$0]$ m$,//$ Signed input

input wire signed $[3$:$0]$ x$,//$ Signed input

input wire signed $[3$:$0]$ c$,//$ Signed input

input wire valid$\_$in$,//$ Inputs valid

output reg signed $[8$:$0]$ y$,//$ Signed output

output reg y$\_$valid $//$ Y valid, driven by design

$)$;

reg signed $[8$:$0]$ product$\_$reg; $//$ Pipeline register for product

reg signed $[8$:$0]$ sum$\_$reg; $//$ Pipeline register for sum

$//$ Stage $1$: Multiplier pipeline stage

always @$($posedge clk or negedge rst$\_$n$)$ begin

if $(!$rst$\_$n$)$

product$\_$reg b$0$; $//$ Reset$8$ product register

else if $($valid$\_$in$)$

product$\_$reg m $*$ x; $//$ Calculate product

end

$//$ Stage $2$: Adder pipeline stage

always @$($posedge clk or negedge rst$\_$n$)$ begin

if $(!$rst$\_$n$)$

sum$\_$reg b$0$; $//$ Reset sum register

else if $($valid$\_$in$)$

sum$\_$reg product$\_$reg $+$ c; $//$ Calculate sum

end

$//$ Output and valid signal assignment

always @$($posedge clk or negedge rst$\_$n$)$ begin

if $(!$rst$\_$n$)$ begin

y b$0$; $//$ Reset output

y$\_$valid b$0$; $//$ Reset valid signal

end

else if $($valid$\_$in$)$ begin

y sum$\_$reg; $//$ Assign output

y$\_$valid b$1$; $//$ Set valid signal

endmodule tb$\_$line$($

$)$;

reg clk;

reg rst$\_$n;

wire signed $[3$:$0]$ m;

wire signed $[3$:$0]$ x;

wire signed $[3$:$0]$ c;

wire signed $[8$:$0]$ y;

wire signed $[8$:$0]$ tb$\_$y;

reg valid$\_$in;

wire y$\_$valid;

reg $[3$:$0]$ addr$\_$in$,$ addr$\_$y;

line dut $(.*)$;

rom #$(.$addr$\_$width $(4),.$data$\_$width $(4),.$init$\_$file$("$m$.$dat"$))$

m$\_$mem$($

$.$addr$($addr$\_$in$),$

$.$data $($m$)$

$)$;

rom #$(.$addr$\_$width $(4),.$data$\_$width $(4),.$init$\_$file$("$x$.$dat"$))$

x$\_$mem$($

$.$addr$($addr$\_$in$),$

$.$data $($x$)$

$)$;

rom #$(.$addr$\_$width $(4),.$data$\_$width $(4),.$init$\_$file$("$c$.$dat"$))$

c$\_$mem$($

$.$addr$($addr$\_$in$),$

$.$data $($c$)$

$)$;

rom #$(.$addr$\_$width $(4),.$data$\_$width $(9),.$init$\_$file$("$y$.$dat"$))$

y$\_$mem$($

$.$addr$($addr$\_$y$),$

$.$data $($tb$\_$y$)$

$)$;

always #$5$ clk $=$ ~clk;

$//$integer file$\_$handle;

initial

begin

$//$file$\_$handle $=$ $fopen$("$output$.$txt$","$w$")$;

clk $=0$;

rst$\_$n $=1\text{'}$h$0$;

valid$\_$in $=0$;

#$73$ rst$\_$n $=1\text{'}$h$1$;

#$17$;

addr$\_$in $=4\text{'}$h$0$;

#$20$;

valid$\_$in $=1$;

for $($integer i $=0$; i $<mtext\; id="EditorElement\_621123"></mtext><mn\; id="EditorElement\_621124">1</mn><mn\; id="EditorElement\_621125">6</mn>$; i $=$ i $+1)$

begin

#$10$;

$//$assert $($y $==$ tb$\_$y$)$;

addr$\_$in $=$ addr$\_$in $+1$;

end

valid$\_$in $=0$;

$//$#$50$;

$//$$fclose$($file$\_$handle$)$;

end

always$\_$ff @ $($posedge clk$)$

begin

if $(!$rst$\_$n$)$

begin

addr$\_$y #$0\mathrm{.}14\text{'}$h$0$;

end

else if $($y$\_$valid$)$

begin

$//$$fwrite$($file$\_$handle, $"\%$b

$",$ y$)$;

assert $($y $==$ tb$\_$y$)$

else $fatal$("$y not equal to tb$\_$y$")$;

addr$\_$y #$0\mathrm{.}1$ addr$\_$y $+1$;

end

end

endmodule