Here is the (a) part

b) As opposed to the 1-hot convention presented in class, the 0-cold logic decoder works the same way as the decoder in (a) but with all outputs inverted. In this case, the decoded output produces one logic-0, and Ts for all others. The symbol is as follows: S2 S1 S0 3.8 3 p Decoder 4 o Modify the design from part (a) to work with the 0-cold logic decoder and implement the same function from (a). Why would the 0-cold decoder be better suited for a CMOS application