Heyyyy! I am stuck with this question and hw due in 1 hour, so pleaseeeeeeeee help. Thank youuuuuu!!!!
// 2 3 // RCA4.SV This design will add two 4-bit vectors // plus a C in to produce a sum and a C out// 5 (3:0) module RCA input input output output (3:0) A,B, Cin, 8, Coul // two 4-bit vectors to be added // An optional C in bit // 4-bit Sum // and C out Correct unvectored implementation // Declare any internal signals as type logie // logic ci, C2, C3; FA FAO (-A (A[0]), FA FAl(.A (A[1]), FA FA2 (-A (A[2]), FA IFA3 (.A (A[3]), B (B[0]), .cin (cin), .S(S[0]), B(B[1]), .Cin(Cl), .3(3[1]), B (B[2]), .cin (C2), 5(S[2]), B(B[3]), .Cin(C3), .3(3[3]), Cout (C1)); Cout(C2)); Cout (C3)); Cout (Cout)); // Implement Full Adder as structural verilog // 25 endmodule 3.3 Vectored Instantiation...A smarter way 1. Imagine if I had asked you to implement a 64-bit RCA adder using 64 copies of your FA cell? Would be pretty tedious right? 2. Prof. Lipasti presented a smarter way of doing multiple instantiations of a block. A "vectored" way of doing it. 3. Copy your RCA4.sv block and call it RCA4_smarter.sv. Modify this block to use the smarter vectored way of instantiating the 4 copies of FA. You do not have to simulate it, but submit your file RCA4_smarter.sv. // // RCA4.5 This design will add two 4-bit vectors // plus a C in to produce a sum and a cout:// [3:0] module RCA input input output output A,B, Cin, S, Cout [3:0) // two 4-bit vectors to be added // An optional C in bit // 4-bit Sum // and C out Wrong Vectored implementation; what did I do wrong? // Declare any internal signals as type logie // logic Ci[3:0]; logic Co[3:01: assign Ci[0]= Cin; assign Ci[1]= CO[0]: assign Ci[2]= Co[1]; assign Ci [3] = CO[2]; assign Co[0]=Ci[1]; assign Co[1]=i[2]; assign Co[2]=Ci[3]; assign Co[3]=Cout; FA IFA[3:01 (.A (A[3:0]), .B(B[3:0]), .Cin (Ci [3:0]), S(S[3:0]), .Cout(Co[3:0])); // Implement Full Adder as structural verilog // endmodule // 2 3 // RCA4.SV This design will add two 4-bit vectors // plus a C in to produce a sum and a C out// 5 (3:0) module RCA input input output output (3:0) A,B, Cin, 8, Coul // two 4-bit vectors to be added // An optional C in bit // 4-bit Sum // and C out Correct unvectored implementation // Declare any internal signals as type logie // logic ci, C2, C3; FA FAO (-A (A[0]), FA FAl(.A (A[1]), FA FA2 (-A (A[2]), FA IFA3 (.A (A[3]), B (B[0]), .cin (cin), .S(S[0]), B(B[1]), .Cin(Cl), .3(3[1]), B (B[2]), .cin (C2), 5(S[2]), B(B[3]), .Cin(C3), .3(3[3]), Cout (C1)); Cout(C2)); Cout (C3)); Cout (Cout)); // Implement Full Adder as structural verilog // 25 endmodule 3.3 Vectored Instantiation...A smarter way 1. Imagine if I had asked you to implement a 64-bit RCA adder using 64 copies of your FA cell? Would be pretty tedious right? 2. Prof. Lipasti presented a smarter way of doing multiple instantiations of a block. A "vectored" way of doing it. 3. Copy your RCA4.sv block and call it RCA4_smarter.sv. Modify this block to use the smarter vectored way of instantiating the 4 copies of FA. You do not have to simulate it, but submit your file RCA4_smarter.sv. // // RCA4.5 This design will add two 4-bit vectors // plus a C in to produce a sum and a cout:// [3:0] module RCA input input output output A,B, Cin, S, Cout [3:0) // two 4-bit vectors to be added // An optional C in bit // 4-bit Sum // and C out Wrong Vectored implementation; what did I do wrong? // Declare any internal signals as type logie // logic Ci[3:0]; logic Co[3:01: assign Ci[0]= Cin; assign Ci[1]= CO[0]: assign Ci[2]= Co[1]; assign Ci [3] = CO[2]; assign Co[0]=Ci[1]; assign Co[1]=i[2]; assign Co[2]=Ci[3]; assign Co[3]=Cout; FA IFA[3:01 (.A (A[3:0]), .B(B[3:0]), .Cin (Ci [3:0]), S(S[3:0]), .Cout(Co[3:0])); // Implement Full Adder as structural verilog // endmodule
