Hi I need help completing the timing diagram

CDA3201. Intro to Logic Design Lab Assignment Name: Grade 100 4) [40] Consider the following sequential circuit with two positive-edge-triggered JK flip-flops Q2 Q2 12 CK K2 Q2 CLR Clock 4.a) [4] Trace the timing diagram for the above circuit by hand. CLR Clock JI 01 J2 K2 Q2