Hi, please explain your answering for this questions espacilly 1,2,3. Thank you for your time!

Page of 12zOOM 4. Consider the 5-stage single-issued pipelined MIPS datapath consisting of Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), and Write-Back (WB). (10 points) You are given the following MIPS instruction sequence $s0 to $s3 -56, 30, 30, 7 # $t0 to $t4-7, 7, 7, 7, 7 add $to, Ss0, s0 Penn State University School of Electrical Engineering and Computer Science Page 11 of 12 and $ti, to, ssl sub $t3, to, $s3 srl $t4, to, 2 Start numbering the cycles with 1 when the add instruction enters the IF stage For part i. to iii. assume that the datapath is broken and there is no forwarding and no stalling. Page of 12zOOM 4. Consider the 5-stage single-issued pipelined MIPS datapath consisting of Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), and Write-Back (WB). (10 points) You are given the following MIPS instruction sequence $s0 to $s3 -56, 30, 30, 7 # $t0 to $t4-7, 7, 7, 7, 7 add $to, Ss0, s0 Penn State University School of Electrical Engineering and Computer Science Page 11 of 12 and $ti, to, ssl sub $t3, to, $s3 srl $t4, to, 2 Start numbering the cycles with 1 when the add instruction enters the IF stage For part i. to iii. assume that the datapath is broken and there is no forwarding and no stalling