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Hints: -function to create required delay void delay(unsigned intmsec ) // Delay function { inti,j ; for(i=0;i for(j=0; j } - Equation to derive analog

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Hints:

-function to create required delay

void delay(unsigned intmsec ) // Delay function

{

inti,j ;

for(i=0;i

for(j=0; j

}

- Equation to derive analog value read

Vanalog= ADC code *LSB in decimal

Full scale = 5V

N=8 bits

LSB= Full scale/2N

N=8

Full scale=5-0=5 (for 5V VCC)

ADC code: 00000000 to 11111111 in binary

Bit 7 Bito TCON Register 3. Answer all the questions given below (a) What are the two main steps for analog to digital conversion? Show that the quantization error increases as the range of voltage levels to be sensed increases. Use 3 bit ADC as an example [2.5+2.5] (b) Consider the following 8051 interfacing problem. (1+1+1+1+1] +5V 8051 ADC0804 P2.5 P2.6 RD WR Vcc CLK R CLK IN P1.0 DO : Vin(+) Vin(-) 10k POT A GND Vref/2 D GND P1.7 D7 P2.7 INTR CS The delay between consecutive analog to digital conversion will be dynamically adjusted. If the analog reading (Vanalog) goes >= VCC/2, delay is 40 ms while if goes

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