Question
How can I display a simple blackjack game on VGA with Verilog? Here is my code so far: `timescale 1ns / 1ps module vga_display( input
How can I display a simple blackjack game on VGA with Verilog? Here is my code so far:
`timescale 1ns / 1ps
module vga_display(
input wire dclk, //pixel clock: 25MHz input wire clr, //asynchronous reset output wire hsync, //horizontal sync out output wire vsync, //vertical sync out
output reg [2:0] red, //red vga output
output reg [2:0] green, //green vga output
output reg [1:0] blue //blue vga output );
// video structure constants parameter hpixels = 800;// horizontal pixels per line parameter vlines = 521; // vertical lines per frame parameter hpulse = 96; // hsync pulse length parameter vpulse = 2; // vsync pulse length parameter hbp = 144; // end of horizontal back porch parameter hfp = 784; // beginning of horizontal front porch parameter vbp = 31; // end of vertical back porch parameter vfp = 511; // beginning of vertical front porch
reg [9:0] hc; reg [9:0] vc; reg [1:0] pxclk;
wire inH = (hc < 640); wire inV = (vc < 480); wire inDisplay = inH && inV;
always @ (posedge clk) pxclk = pxclk + 1; wire pclk; assign pclk = pxclk[1]; // 25MHz Pixel Clock
always @(posedge dclk or posedge clr) begin // reset condition if (clr == 1) begin hc <= 0; vc <= 0; end else begin // keep counting until the end of the line if (hc < hpixels - 1) hc <= hc + 1; else // When we hit the end of the line, reset the horizontal // counter and increment the vertical counter. // If vertical counter is at the end of the frame, then // reset that one too. begin hc <= 0; if (vc < vlines - 1) vc <= vc + 1; else vc <= 0; end end end
assign hsync = (hc < hpulse) ? 0:1; assign vsync = (vc < vpulse) ? 0:1;
always @(*) begin // first check if we're within vertical active video range if (vc >= vbp && vc <= vfp) begin if(hc <= hbp || hc >= hfp) begin red = 3'b111; green = 0; blue = 0; end if (!inDisplay) begin red = 0; green = 0; blue = 0; end end
endmodule
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