How is the 10 bit address used in an I2C bus? Why is the rd/wr bit sent with the first address byte and not the second? What is the use of clock stretching in an IC bus? How is it implemented? In case of a multi-master bus, how is a collision caused by two masters taking over the bus simultaneously detected? Why is the multiply driven SCL not distorted too much in case of a collision? How is arbitration carried out? Why does the master issuing a lower address win the arbitration?