Question
How long will the following code fragment take to issue on an in-order superscalar processor with two execution units, where all instructions have latencies of
How long will the following code fragment take to issue on an in-order superscalar processor with two execution units, where all instructions have latencies of 1 cycle and any execution unit can execute any instruction? LD r1, (r2) SUB r4, r5, r6 ADD r3, r1, r7 MUL r8, r3, r3 ST (r11), r4 ST (r12), r8 ADD r15, r14, r13 SUB r10, r15, r10 ST (r9), r10
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The World Wide Web And Databases International Workshop Webdb 98 Valencia Spain March 27 28 1998 Selected Papers Lncs 1590
Authors: Paolo Atzeni ,Alberto Mendelzon ,Giansalvatore Mecca
1st Edition
