How long will the following code fragment take to issue on an in-order superscalar processor with three execution units, where all instructions have latencies of 1 cycle and any execution unit can execute any instruction?

LD r1, (r2)

SUB r4, r5, r6

ADD r3, r1, r7

MUL r8, r3, r3

ST (r11), r4

ST (r12), r8

ADD r15, r14, r13

SUB r10, r15, r10

DIV r11, r7, r3

SUB r3, r4, r8

OR r10,r7, r0

ASH r2, r14, r6