how many cycles does a Load instruction require on P1? How many cycles does a ALU instruction require on P2?

Operation	Instruction Count
ALU	550
load	300
store	500
branch	400

opperation	p1	p2
ALU	1
Load		4
store	2	3
branch	3	3

P1: 6% instruction cache miss rate, a 2% data cache miss rate,and a 150 cycle miss penalty. 11.082 on Processor1

P2: 3% instruction cache miss rate, a 5% data cache miss penalty, and a 125 cycle miss penalty. 5.679 on Processor 2.

how many cycles does a Load instruction require on P1? How many cycles does a ALU instruction require on P2?