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I. (a) Implement the following gates with minimum number of transistors: (15%) 3-input NAND: Y-ABC 4-input NOR: Y = A + B + C +

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I. (a) Implement the following gates with minimum number of transistors: (15%) 3-input NAND: Y-ABC 4-input NOR: Y = A + B + C + D 3-input AOI: Y=AB + C

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