I dont know how to do them If you could explain it I would gladly appreciate it.

Using only a T flip-flop and 3 NAND gates, implement a JK flip-flop. 4. The circuit below contains a D-latch, a positive edge triggered D flip-flop and a negative edge triggered D flip-flop. Given the waveforms for X and clk, draw the waveforms for Y1, Y2 and Y3, assuming no delay. Y1 Y2 Y3 (o 0 CLK CLK