I give part $1$ to you and thise is part $2$ about datastructer proj please help me to solve it $!$

And i want to give i another page the last part

In this

Clocking the register file

The register file that you created in the first part was a combinational circuit. This causes some serious problems if$,$ for example, address $2$ and address $3$ are the same. The circuit would read output $2$ from the location referenced by address $2,$ at the same time that the input is over$-$writing that of

These problems can be solved by synchronising the register file to a clock. You will need to add an extra input named clock, and give the register file the following behaviour:

On the rising edge of the clock:

Output $1$ produces the item within the register file that is address by Address $1.$

Input is used to supply a value that is written into the location addressed by Address $3.$

$3$

Under all other circumstances

the outputs are held constant at the values they assumed during the last rising edge of the clock. You should check your design thoroughly, and in particular make sure that it behaves sensibly when the address for the input is the gam address of $0$ ofe of the outp

Enabling the register file

The register file that you created is always sensitive to its inputs, even when the inputs have garbage values. This can case poble values. This can cause problems because when the simulation initializes $($which corresponds to the real hardware being switched on$)$ all the values of the logic signals initializes to some random garbage value. Give the register file an enable input. When the enable input $=1$ the register file will operate normally. Otherwise the register file will ignore its inputs, and will not update its outputs. Creating the core of the microprocessor like this $($module mp top$)$:

Test out your design by supplying machine instructions to it$,$ and check that the operation performed is correct. Make sure you understand the timing of instructions, and in particular the relationship between the clock cycle on which the instruction occurs, and the clock cycle on which the appropriate result is the clock cycle on w

Main Modules templates

In order to ease the ability to test your design, you need to stick the following modules definition. If you don't stick to the modules definition, then testing your des

Machine instructions are

instructions is as follows: The first $6$ bits identify the opcode

The next $5$ bits identify first source register

The next $5$ bits identify destination register

The final $11$ bits are unused

So$,$ for example, if you want to add the contents of register $1$ and register $2$ and put the result into register

The first $6$ bits supply the opcode for the as follows:

The next $5$ bits would address register $1,$ and the next $5$ would address register $2-$ The next $5$ bits address register $3.$

The remaining bits are unused, and should be set to zero.

low otherwise.

endmodule

hodule reg$\_$file $($clk$,$ valid$\_$opcode, addr$1,$ addr$2,$ addr$3,$ in$,$ outl, out$2)$; input clk;

$[4$:$0]$ addr$1,$ addr$2,$ addr$3$;

re

$131$:$0$

out$1,$ out$2$;

Running a program $($Testing your design$)$

Now create a stream of machine instructions that will act as a small program. The program must act as

fllows:

$1-$ Create an array of instructions.

$2-$ Include at least one instruction for each of the provided opcodes.

instruction and result $($output$)$

$4-$ For each instruction calculate the expected result, then compare the expected value with your

$5-$ If any instruction fails, then test fails, else test passes

Synchronising the data

All parts of the design that are synchronized to the clock should use only the rising edge of the clock. If you use both the rising edge and the falling edge, then it's much easier to do the design in simulation, but the real life hardware would be very expensive and complicated substantial number of marks if you use both edges of the clock.