I JUST NEED ANSWER, NO NEED EXPLANATION. THANKS

Q1) Design a Full Adder with gate level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output.) Q2) Design a 2x4 Decoder with gate level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output.) A1 Y3 Y2 Y1 B YO E