I just need the appropriate test bench with the code for msgchk below. (Code is in Verilog)

problem you will create a testbench for the module msgchk whose Verilog code is below. (Only the module port declaration is needed for this problem.) Your testbench should provide the c1k,s, and d inputs and display the e and p outputs. clk, should have a period of 40ns and should be initially high with the first falling edge at 20ns