I JUST NEED THE PORT MAP AND THE TEST BENCH TO CREATE THE TOP MODULE USING ALL THE 3 SUBMODULES.

Help in VHDL programming. Please help me create the PORT MAP FOR THE TOP MODULE WHICH CONSISTS OF 3 OTHER MODULES.

TOP MODULE(HELP ME CREATE THIS USING THE INPUTS AND THE OUTPUTS FROM INDIVUDUAL SUB MODULES):

GATES MODULES:

MUX8TO1:

DISPLETTER:

GETTING IT ALL TOGETHER (TOP MODULE DESIGN) Inputs S2 So, Top Module MUXsto1 MUX OUT 7 seg Gates Disp Letter display LED Outputs Project CheckGatesSystem op Module) Gates (Module 1) MUX8to1 (Module 2) DispLetter (Module 3) GETTING IT ALL TOGETHER (TOP MODULE DESIGN) Inputs S2 So, Top Module MUXsto1 MUX OUT 7 seg Gates Disp Letter display LED Outputs Project CheckGatesSystem op Module) Gates (Module 1) MUX8to1 (Module 2) DispLetter (Module 3)