I mainly need the last two queations.

You are a designer who is tasked with implementing in hardware a support for the following EVAL instruction in a given ISA:EVAL RD$,$ RS$1,$ RS$2$which operates on the content of two $16$ bit source registers RS$1$ and RS$2$ and generates a $32$ bit result in the destination register RD$,$ according to the following formulation:RD $=($RS$1+$ RS$2)*($RS$1-$ RS$2)$where $*$ is the multiplication operation. Suggest a hardware architecture that generates the result in RD:Over a single clock cycleOver two clock cyclesAssume you have space to accommodate only a $32$ bit adder, how many clock cycles your implementation will require to generate the result in RD $($roughly$)?$ Implement the option $1.$A above in Verilog and report the clock frequency when realized on FPGA using Intel device EP$4$CE$115$F$29$C$7.$ What is the total CPU time for a program that consists of N instructions all similar to the instruction above? Assume you implemented the option $1.$B above in Verilog and the reported clock frequency when realized on FPGA using Intel device EP$4$CE$115$F$29$C$7$ is F Hz$.$ What is the total CPU time for a program that consists of N instructions all similar to the instruction above?