I need a testbench for this prgram on VHDL quartus prime intel

Tibrary ieee; use ieee. std_logic_1164, a 11; use ieee. numeric_std.a71; Garchitecture counter of counter_project is Lsigna1 count_i: integer: =(k1); begin Gprocess(reset, c7k, ce) l begin bif reset = ' 0 " then if rising_edge(c 7k ) then if ce = " 1 " then count_i