I need a Verilog code of the problem along with a testbench code and screenshot of output waveform.

Using the specification, create a Veilog implementation of an AMBA APB slave with a 32-bit data interface. 4 address locations, each with read and write capability. APB Slave PCLK PADDRI1:0] PWAITE PSEL PWDATAI31:0] PRDATA 31:0 PREADY Submit the Verilog description and a screen shot of the wave trace showing the cormect operation Using the specification, create a Veilog implementation of an AMBA APB slave with a 32-bit data interface. 4 address locations, each with read and write capability. APB Slave PCLK PADDRI1:0] PWAITE PSEL PWDATAI31:0] PRDATA 31:0 PREADY Submit the Verilog description and a screen shot of the wave trace showing the cormect operation