I need help answering these questions thanks!

Question 1. Assume that the MIPS stages have these latencies (in ps): Instruction Register Execute Data Register Memory Read Memory Write 200 100 100 250 150 a) What is the clock cycle time for a nonpipelined processor? [5 Points] b) What is the clock cycle time for a pipelined processor? [5 Points] c) Find the total latency for each of the R-type, lw, sw, and be instructions for both nonpipelined and pipelined processor. The total latency comprises of the total of all active phases. Ignore the PC write time. [15 Points) d) Which instruction from part c) above has the shortest total latency in nonpipelined and pipelined processor? What is its latency in ps? [5 Points]