I need help for my Microprocessor Lab. We are using DE1-SoC development boards by Altera, Alter'as Quartus 16, abd Intel FGPA Monitor Program with GNU assemblers.

Part 2

1. Using the directions from Part 1, make a new project.
2. Using the ADD instruction, modify the simple_program.s file to read the value of the switches, and multiply it by two (by adding itself to itself) and output that value to the LEDs.
3. Using the single step function mentioned above, step through each instruction, noting how the values in each register changes, and how the LEDs are now acting different then before your modification.
4. Demonstrate a successful build, upload, and functionality to your instructor.

Lab Report

Complete a lab report, using the ECE Laboratory Report Guidelines found on Canvas. Make sure to include enough relevant information, such as equipment including board number, so someone could reproduce your lab. You should not simply copy the instructions in this document. Include your final program you wrote in Part 2 as an appendix in your report, and in the body of your report, include a screenshot from your computer showing a successful compile and upload (do not crop your screenshot! I want to see your entire desktop).

In your report, address the following questions:

• What is the point of the address_map_arm.s file?
• How would a user access the registers without the address_map_arm.s file? (Give an example instruction using this method).

Simple.program.s

.include "address_map_arm.s"

.text

.global _start

_start:

LDR R1, =LEDR_BASE /* Address of red LEDs. */

LDR R2, =SW_BASE /* Address of switches. */

LOOP: LDR R3, [R2] /* Read the state of switches.*/

STR R3, [R1] /* Display the state on LEDs. */

B LOOP

.end

Address_map_arm.s

/* This files provides address values that exist in the system */

/* Memory */

.equ DDR_BASE, 0x00000000

.equ DDR_END, 0x3FFFFFFF

.equ A9_ONCHIP_BASE, 0xFFFF0000

.equ A9_ONCHIP_END, 0xFFFFFFFF

.equ SDRAM_BASE, 0xC0000000

.equ SDRAM_END, 0xC3FFFFFF

.equ FPGA_ONCHIP_BASE, 0xC8000000

.equ FPGA_ONCHIP_END, 0xC803FFFF

.equ FPGA_CHAR_BASE, 0xC9000000

.equ FPGA_CHAR_END, 0xC9001FFF

/* Cyclone V FPGA devices */

.equ LEDR_BASE, 0xFF200000

.equ HEX3_HEX0_BASE, 0xFF200020

.equ HEX5_HEX4_BASE, 0xFF200030

.equ SW_BASE, 0xFF200040

.equ KEY_BASE, 0xFF200050

.equ JP1_BASE, 0xFF200060

.equ JP2_BASE, 0xFF200070

.equ PS2_BASE, 0xFF200100

.equ PS2_DUAL_BASE, 0xFF200108

.equ JTAG_UART_BASE, 0xFF201000

.equ JTAG_UART_2_BASE, 0xFF201008

.equ IrDA_BASE, 0xFF201020

.equ TIMER_BASE, 0xFF202000

.equ TIMER_2_BASE, 0xFF202020

.equ AV_CONFIG_BASE, 0xFF203000

.equ PIXEL_BUF_CTRL_BASE, 0xFF203020

.equ CHAR_BUF_CTRL_BASE, 0xFF203030

.equ AUDIO_BASE, 0xFF203040

.equ VIDEO_IN_BASE, 0xFF203060

.equ ADC_BASE, 0xFF204000

/* Cyclone V HPS devices */

.equ HPS_GPIO1_BASE, 0xFF709000

.equ I2C0_BASE, 0xFFC04000

.equ I2C1_BASE, 0xFFC05000

.equ I2C2_BASE, 0xFFC06000

.equ I2C3_BASE, 0xFFC07000

.equ HPS_TIMER0_BASE, 0xFFC08000

.equ HPS_TIMER1_BASE, 0xFFC09000

.equ HPS_TIMER2_BASE, 0xFFD00000

.equ HPS_TIMER3_BASE, 0xFFD01000

.equ FPGA_BRIDGE, 0xFFD0501C

/* ARM A9 MPCORE devices */

.equ PERIPH_BASE, 0xFFFEC000 /* base address of peripheral devices */

.equ MPCORE_PRIV_TIMER, 0xFFFEC600 /* PERIPH_BASE + 0x0600 */

/* Interrupt controller (GIC) CPU interface(s) */

.equ MPCORE_GIC_CPUIF, 0xFFFEC100 /* PERIPH_BASE + 0x100 */

.equ ICCICR, 0x00 /* CPU interface control register */

.equ ICCPMR, 0x04 /* interrupt priority mask register */

.equ ICCIAR, 0x0C /* interrupt acknowledge register */

.equ ICCEOIR, 0x10 /* end of interrupt register */

/* Interrupt controller (GIC) distributor interface(s) */

.equ MPCORE_GIC_DIST, 0xFFFED000 /* PERIPH_BASE + 0x1000 */

.equ ICDDCR, 0x00 /* distributor control register */

.equ ICDISER, 0x100 /* interrupt set-enable registers */

.equ ICDICER, 0x180 /* interrupt clear-enable registers */

.equ ICDIPTR, 0x800 /* interrupt processor targets registers */

.equ ICDICFR, 0xC00 /* interrupt configuration registers */