I need help with A. As well as the bonus. Not exactly sure how to make this circuit.

Homework 6 Due: Wednesday, February 28, 2018 CS2170: Rex 5 pts + Bonus 5 pts A. Decoder Expansion (5 pt) Use LogicWorks to construct a simulation of a 5x32 decoder. Build your decoder with one 2x4 decoder and four 3x8 decoders (found in the Simulation Logic.clflibrary). Use the 2x4 decoder to select which of the 3x8 decoders is enabled. Label your inputs A0, Al first three inputs as the selector values for the 3x8 decoders. Use A3and 44 for the selectors for the 2x4 decoder. Label your 13, 44 where A0 is the least significant input digit. Use the outputs DO0 to DIF. Remember that LogicWorks uses negative-logic decoders, so you enable decoders with a value of zero on the EN pin. Name you LogicWorks file with your lastname, first initial and hw6a. Use .cet as the file extension (e.g., KingB hw6a.cct). . Bonus! Multiplexer (MUX) Expansion (5 pt) Use LogicWorks to construct a simulation of a 16 x 1 multiplexer. Here are two ways you might do this 1. Construct the MUX out of two 8-to-1 line multiplexers (Mux-8) and a 4-to-1 line multiplexer (Mux-4). You can find these parts in Logic Works in the Simulation Logic.clf library. Set the Enable (EN) pin for each mux to 0. Hint: For the 4-to-1 line multiplexer to use one of the selector inputs and two of the data inputs. The unused ones can be set to 0 Another way to construct the MUX is using 7400-153 dual 4-to-1 line multiplexers. These are actual TTL (Transistor-Transistor Logic) chips you could buy. In LogicWorks they are in the 7400DEVS.CLF library under the name 74 153. Set the GA (enable) and 2. ground) pins to 0. Note that these muxes have two outputs. The selector inputs SI and SO select one line from A0-43 as output YA and one line from BO-B3 as output YB. You will need three 74_153 muxes with the outputs from two of them serving as inputs to the 40-43 pins of a third 74_153 mux (BO-B3 and YB won't be used in the third one) Whichever parts you choose to construct your circuit, your design should select one of the 16 data input lines to be the final output. Label your data inputs as InO to InF. Label your final output as Output. Label your selectors as SO, SI, S2, S3 with SO as the least significant bit. Name you LogicWorks file with your lastname, first initial and hw6b (e.g. RiggsB_hw6b.cct)