I need some help with this lab, please! And I need it quickly, please!

Sequential logic circuits are defined as circuits whose output depends both on the present values of the inputs and the present state of the circuit. Latches are basic sequential circuits whose operation you will investigate with this lab. Instructions/ Deliverables Part One - Place components and simulate the asynchronous (Not Clocked) SR NAND latch by using "add source" for the model (Nand2Delay) given on FSO. The Nand2Delay has a 1 ns propagation delay - Use the following Test Stimulus and capture a screenshot of theSR NAND latch circuit, along with the iSim waveform --simulation for NAND SR latch on lecture slides 7-9 --No Change ClockOne