i need step by step solution for A,B,C,D

I. Show in detail the design of a 128k24-bit RAM using 64k8-bit RAM ICs and any additional required circuitry. In your design, consider the Chip Select (CS) signals to be active high inputs. Also, assume that the 64kx8-bit RAM IC has a shared line for reading and writing and that separate input and output pins are available. II. A fully synchronous sequential circuit based on JK Flip-Flops is provided as in the logic diagram below: The timing parameters for the gates and flip-flops are as follows: Inverter: tpd=0.10ns. XOR gate: tp=0.45ns. AND gate: tpd=0.15ns. Flip-Flop: tp=0.50ns,tc=0.15ns,tM=0.05ns. OR gate: tpd=0.25ns. Answer each of the Questions 1) to 4) below. You first need to write the equation for the delay before calculating the corresponding numerical value. a. Find the longest path delay from an external circuit input to the positive edge of the clock. b. Find the longest path delay from the positive edge of the clock to the external output. 1/2 c. Find the longest path delay from the positive edge of the clock to the next positive edge of the clock. d. Determine the maximum frequency of operation of the circuit in megahertz (MHz)