I need the gate level modeling in verilog for the following state machine, also I need the gate level modelingin verilog for the counter that is used. The modeling should be done acording to the instructions and the provided schematics please. PLEASE PROVIDE ALL THE verilog CODE, divided by modules.

Instructions

Where $`$cnt$`$ is the output of a counter that resets to $0$ if the $`$cnt$\_$rst$`$ signal is high, and counts as long as $`$cnt$\_$rst$`$ is low and $`$cnt$\_$en$`$ is high: