Question: I need these fix the first mode isn't showing on the opcode and i need a ALC for the opcode and enable to go to

I need these fix the first mode isn't showing on the opcode and i need a ALC for the opcode and enable to go to four segment and led display. the input are a[0:7] and b[8:16]. module calculator_fsm (
input clk,// Clock signal
input btn_mode1,// Button for Mode 1(Arithmetic)
input btn_mode2,// Button for Mode 2(Bitwise)
input [1:0] btn_sel, // Button to select operation
output reg [2:0] opcode, //3-bit opcode for ALU
output reg mode, //1-bit mode (0= Arithmetic, 1= Bitwise)
output reg alu_enable // Enable signal for ALU
);
// State Encoding
localparam MODE_1=1'b0; // Mode 1: Arithmetic operations
localparam MODE_2=1'b1; // Mode 2: Bitwise operations
// State register to store current mode
reg current_mode;
reg btn_mode1_last, btn_mode2_last; // To detect button press edge for mode toggle
// FSM State Transition
always @(posedge clk) begin
// Detect button press to toggle between modes
if (btn_mode1 && !btn_mode1_last) begin
current_mode = MODE_1; // Select Mode 1(Arithmetic)
end else if (btn_mode2 && !btn_mode2_last) begin
current_mode = MODE_2; // Select Mode 2(Bitwise)
end
btn_mode1_last = btn_mode1; // Update button state for mode1
btn_mode2_last = btn_mode2; // Update button state for mode2
end
// Output and operation selection based on current mode and btn_sel
always @(*) begin
// Default values
alu_enable =0; // Initially disable ALU
case (current_mode)
MODE_1: begin
mode =0; // Arithmetic Mode
case (btn_sel)
2'b00: begin
opcode =3'b000; // Addition
alu_enable =1; // Enable ALU
end
2'b01: begin
opcode =3'b001; // Subtraction
alu_enable =1; // Enable ALU
end
2'b10: begin
opcode =3'b010; // Multiplication
alu_enable =1; // Enable ALU
end
2'b11: begin
opcode =3'b011; // Division
alu_enable =1; // Enable ALU
end
default: begin
opcode =3'b000; // Default to Addition
alu_enable =1; // Enable ALU
end
endcase
end
MODE_2: begin
mode =1; // Bitwise Mode
case (btn_sel)
2'b00: begin
opcode =3'b100; // AND
alu_enable =1; // Enable ALU
end
2'b01: begin
opcode =3'b101; // OR
alu_enable =1; // Enable ALU
end
2'b10: begin
opcode =3'b110; // Shift Left
alu_enable =1; // Enable ALU
end
2'b11: begin
opcode =3'b111; // Shift Right
alu_enable =1; // Enable ALU
end
default: begin
opcode =3'b100; // Default to AND
alu_enable =1; // Enable ALU
end
endcase
end
default: begin
mode =0;
opcode =3'b000;
alu_enable =0;
end
endcase
end
endmodule
module calculator_fsm_tb;
// Declare testbench signals
reg clk; // Clock signal
reg btn_mode1, btn_mode2; // Buttons for mode selection
reg [1:0] btn_sel; // Button to select operation
wire [2:0] opcode; // ALU opcode output
wire mode; // Mode output (0= Arithmetic, 1= Bitwise)
wire alu_enable; // ALU enable output
// Instantiate the calculator FSM
calculator_fsm uut (
.clk(clk),
.btn_mode1(btn_mode1),
.btn_mode2(btn_mode2),
.btn_sel(btn_sel),
.opcode(opcode),
.mode(mode),
.alu_enable(alu_enable)
);
// Clock generation
always begin
#5 clk = ~clk; // Generate a clock with a period of 10 time units
end
// Testbench stimulus to check opcode for both modes
initial begin
// Initialize inputs
clk =0;
btn_mode1=0;
btn_mode2=0;
btn_sel =2'b00; // Test Addition (opcode should be 3'b000)
// Test Mode 1(Arithmetic)
btn_mode1=1; // Select Arithmetic mode
#10;
btn_mode1=0;
#10;
// Test different arithmetic operations
btn_sel =2'b00; // Addition (opcode should be 3'b000)
#20;
btn_sel =2'b01; // Subtraction (opcode should be 3'b001)
#20;
btn_sel =2'b10; // Multiplication (opcode should be 3'b010)
#20;
btn_sel =2'b11; // Division (opcode should be 3'b011)
#20;
// Test Mode 2(Bitwise)
btn_mode2=1; // Select Bitwise mode
#10;
btn_mode2=0;
#10;
// Test bitwise operations
btn_sel =2'b00; // AND (opcode should be 3'b100)
#20;
btn_sel =2'b01; // OR (opcode should be 3'b101)
#20;
btn_sel =2'b10; // Shift Left (opcode should be 3'b110)
#20;
btn_sel =2'b11; // Shift Right (opcode should be 3'b111)
#20;
end
endmodule
I need these fix the first mode isn't showing on

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