I posted a question a few minutes ago about sngle cycle cpu Here is the completion of the question in vhdl

thanks

single cycle using the component (control_unit, DataMemory, func_unit, Mux2x1_16bit, reg)

already defined all the components in another window or set of files using Quartus in my laptop

entity func_unit is Port ( a_in : in STD_LOGIC_VECTOR (15 downto 0); b_in : in STD_LOGIC_VECTOR (15 downto 0); data_out : out STD_LOGIC_VECTOR (15 downto 0); fs : in STD_LOGIC_VECTOR (3 downto 0); V,C,N,Z : out std_logic ); end func_unit;

architecture Behavioral of func_unit is signal buffer_value:std_LOGIC_VECTOR(16 downto 0); begin

process (a_in,b_in,fs) begin case fs is -- operators when "0000" => buffer_value <= '0'&a_in; when "0001" => buffer_value <= ('0'&a_in)+1; when "0010" => buffer_value <= ('0'&a_in)+('0'&b_in); when "0011" => buffer_value <= ('0'&a_in)+('0'&b_in)+1; when "0100" => buffer_value <= ('0'&a_in)+not(('0'&b_in)); when "0101" => buffer_value <= ('0'&a_in)+not(('0'&b_in))+1; when "0110" => buffer_value <= ('0'&a_in)-1; when "0111" => buffer_value <= ('0'&a_in); when "1000" => buffer_value <= '0'&(a_in and b_in); when "1001" => buffer_value <= '0'&(a_in or b_in); when "1010" => buffer_value <= '0'&(a_in xor b_in); when "1011" => buffer_value <= '0'& not(a_in); when "1100" => buffer_value <= '0'&b_in; when "1101" => buffer_value <= '0'&('0'&b_in(15 downto 1));--srB when "1110" => buffer_value <= '0'&(b_in(14 downto 0)&'0');--rlB when others => buffer_value <= "XXXXXXXXXXXXXXXXX"; end case; end process;

process (buffer_value) begin if (buffer_value(15 downto 0)="0000000000000000") then Z<='1'; else Z<='0'; end if; end process;

process (a_in,b_in,buffer_value) begin if (a_in(15)='1' and b_in(15)='1' and buffer_value(15)='0') then V<='1'; elsif (a_in(15)='0' and b_in(15)='0' and buffer_value(15)='1') then V<='1'; else V<='0'; end if; end process;

C<=buffer_value(16); N<=buffer_value(15);

data_out<=buffer_value(15 downto 0);

end Behavioral;

library ieee;

entity single is port( clk : in std_logic ); end single;

architecture Behavioral of single is

signal zero_fill_ara,a_bus_ara,b1_ara,b2_ara,d1_ara,d2_ara,memory_out_ara:std_logic_vector(15 downto 0); signal da,ba,aa:std_logic_vector(2 downto 0); signal fs:std_logic_vector(3 downto 0); signal mb,md,rw,mw:std_logic; signal V,C,N,Z:std_logic;

component Mux2x1_16bit is port( I1 : in std_logic_vector(15 downto 0); I0 : in std_logic_vector(15 downto 0); S : in std_logic; O : out std_logic_vector(15 downto 0) ); end component; component reg is Port ( rw : in STD_LOGIC; da : in STD_LOGIC_VECTOR (2 downto 0); aa : in STD_LOGIC_VECTOR (2 downto 0); ba : in STD_LOGIC_VECTOR (2 downto 0); data_in : in STD_LOGIC_VECTOR (15 downto 0); a_out : out STD_LOGIC_VECTOR (15 downto 0); b_out : out STD_LOGIC_VECTOR (15 downto 0); clk : in STD_LOGIC); end component; component control_unit is port( clk : in STD_LOGIC; V,C,N,Z : in std_logic; zerofill_out: out std_logic_vector(15 downto 0); a_in: in std_logic_vector(15 downto 0); da_out, ba_out, aa_out : out std_logic_vector(2 downto 0); mb_out, md_out, rw_out, mw_out: out std_logic; fs_out: out std_logic_vector(3 downto 0) ); end component; component func_unit is Port ( a_in : in STD_LOGIC_VECTOR (15 downto 0); b_in : in STD_LOGIC_VECTOR (15 downto 0); data_out : out STD_LOGIC_VECTOR (15 downto 0); fs : in STD_LOGIC_VECTOR (3 downto 0); V,C,N,Z : out std_logic ); end component; component DataMemory is Port ( MW : in STD_LOGIC; Data_in : in STD_LOGIC_VECTOR (15 downto 0); Address : in STD_LOGIC_VECTOR (15 downto 0); Data_out : out STD_LOGIC_VECTOR (15 downto 0); clk : in std_LOGIC); end component;

begin

muxb:Mux2x1_16bit port map( I1 => zero_fill_ara, I0 =>b1_ara, S =>mb, O =>b2_ara ); muxd:Mux2x1_16bit port map( I1 =>memory_out_ara, I0 =>d1_ara, S =>md, O =>d2_ara );

reg_file:reg Port map( rw =>rw, da =>da, aa =>aa, ba=>ba, data_in =>d2_ara, a_out =>a_bus_ara, b_out =>b1_ara, clk=>clk );

control:control_unit port map( clk =>clk, zerofill_out=>zero_fill_ara, da_out=>da, ba_out=>ba, aa_out=>aa, mb_out=>mb , md_out=>md , rw_out=>rw , fs_out=>fs, mw_out=>mw, V=>V, C=>C, N=>N, Z=>Z, a_in=>a_bus_ara ); alu:func_unit Port map( a_in =>a_bus_ara, b_in =>b2_ara, data_out =>d1_ara, fs =>fs, V=>V, C=>C, N=>N, Z=>Z ); memory:DataMemory Port map( MW => mw, Data_in => b2_ara, Address => a_bus_ara, Data_out => memory_out_ara, clk => clk ); end Behavioral;