I want help in verilog HDL$,$ for each question show the design test and the results

Q$3$: Using counters and other logic devices, design a traffic light that operates as follows: Red

light for $9$ seconds, Orange light for $3$ seconds and green light for $12$ seconds. Assume a clock

frequency of $1Hz.$ Show your work and results by testing the circuit for $60$ seconds

Q$4$: Design a one$-$input, one$-$output serial $2\text{'}$s complementor. The circuit accepts a string of

bits from the input and generates the $2\text{'}$s complement at the output. The circuit can be

reset asynchronously to start and end the operation.

Test your circuit using the following input sequence.

$010111110111100$

Random sequence of your choice.