I want Test bench for this code vhdl

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY clock IS

port(reset,clk,start,stop:in std_logic;

min,sec:out integer);

end clock;

architecture behaviour of clock is

begin

process(reset,clk,start,stop)

variable tempmin,tempsec:integer:=0;

begin

if(reset='1')then

tempmin:=0;

tempsec:=0;

elsif(stop='1')then

min

sec

elsif(start='1')then

if(rising_edge(clk))then

tempsec:=tempsec+1;

if(tempsec=60)then

tempsec:=0;

tempmin:=tempmin+1;

if(tempmin=10)then

tempmin:=0;

end if;

end if;

end if;

end if;

min

sec

end process;

end behaviour;

min sec sec start stopE reset Design a vhdl code a timer capable of running from Omin:00sec to 9min:59sec (figure 2). The circuit must have start, stop, and reset buttons. The outputs must be SSD coded Consider that a reliable 1 Hz clock signal is available min sec sec start stopE reset Design a vhdl code a timer capable of running from Omin:00sec to 9min:59sec (figure 2). The circuit must have start, stop, and reset buttons. The outputs must be SSD coded Consider that a reliable 1 Hz clock signal is available