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The following siruction Verilog modvla kis for a 3 -ble counter. Tha outpurs of tha counter are c2. (most slgnifeont), Cl, and co (leost significont). The mostule contelns three gotes: Two imvaters and 2-input x on gate. The module definitions of the gotes ore gwen as comments in the code. The module dso contioins three D-type Rip-flops (FF). The modile deiinitions of the FF is given as a comment in the code. The following waveform is generated using functional sirnulation for the 3-bit counter above. Hotice that outputs C2,Cl, and CO are grouped together and named "C" and formatted as "Unsigned Decimal". "C2" is most significant and " Co is least significant. Accordingly determine Valuel and Value2? The following siruction Verilog modvla kis for a 3 -ble counter. Tha outpurs of tha counter are c2. (most slgnifeont), Cl, and co (leost significont). The mostule contelns three gotes: Two imvaters and 2-input x on gate. The module definitions of the gotes ore gwen as comments in the code. The module dso contioins three D-type Rip-flops (FF). The modile deiinitions of the FF is given as a comment in the code. The following waveform is generated using functional sirnulation for the 3-bit counter above. Hotice that outputs C2,Cl, and CO are grouped together and named "C" and formatted as "Unsigned Decimal". "C2" is most significant and " Co is least significant. Accordingly determine Valuel and Value2