i want the VERILOG code.

Part I Figure 1(a) shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. If s = 0 the multiplexer's output m is equal to the input x, and if s=1 the output is equal to y. Part (b) of the figure gives a truth table for this multiplexer, and part (c) shows its circuit symbol. wi D co Figure 1: A 2-to-1 multiplexer. The multiplexer can be described by the following Verilog statement: m