I want to get 8 bits counter using this code but don't understand the code and I don't how to change it.

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

ENTITY counter IS

PORT( i_resetBar, i_load : IN STD_LOGIC;

i_clock : IN STD_LOGIC;

o_Value : OUT STD_LOGIC_VECTOR(1 downto 0));

END counter;

ARCHITECTURE rtl OF counter IS

SIGNAL int_a, int_na, int_b, int_nb : STD_LOGIC;

SIGNAL int_notA, int_notB : STD_LOGIC;

COMPONENT enARdFF_2

PORT( i_resetBar : IN STD_LOGIC; i_d : IN STD_LOGIC;

i_enable : IN STD_LOGIC; i_clock : IN STD_LOGIC;

o_q, o_qBar : OUT STD_LOGIC);

END COMPONENT;

BEGIN

-- Concurrent Signal Assignment

int_na <= int_a xor int_b;

int_nb <= not(int_b);

msb: enARdFF_2

PORT MAP (i_resetBar => i_resetBar, i_d => int_na, i_enable => i_load, i_clock => i_clock, o_q => int_a, o_qBar => int_notA);

lsb: enARdFF_2

PORT MAP (i_resetBar => i_resetBar, i_d => int_nb, i_enable => i_load, i_clock => i_clock, o_q => int_b, o_qBar => int_notB);

-- Output Driver o_Value <= int_a & int_b; END rtl;