I wrote a Verilog code to create a module that takes two inputs that are in the form of a 32-bit IEEE 754 single precision standard and adds them, but when I run the following code I get the following errors. I can't figure out why the code is not correct. can you please debug it and write a correct version. -------------------------------THE CODE------------------------------

module math_adder (a,b,addition_of_a_and_b); input [31:0] a,b; output reg [31:0] addition_of_a_and_b; reg [7:0]n; reg result_sig; reg [7:0]result_exp; reg [23:0]result_man; reg sigA; reg sigB; reg [7:0] expA; reg[7:0] expB; reg [22:0] manA; reg [22:0] manB; always @(*)begin sigA = a[31]; sigB = b[31]; expA = a[30:23]; expB = b[30:23]; manA = a[22:0]; manB = b[22:0]; end

always @(*)begin// Extracting The difference between exponents if there is expA = expA-8'd127; expB = expB-8'd127; if(expA > expB)begin n = expA-expB; end else if(expA < expB)begin n = expB-expA; end else if(expA == expB)begin n = 8'b0000_0000; end end always @(*)begin if(expA > expB)begin manB = manB >>n; end else if(expA < expB)begin manA = manA >>n; end end always @(*)begin result_man = manA + manB;// Getting the new mantissa end always @(*)begin if(result_man[23]== 1'b1)begin result_man = result_man >> 1;// If there is an overflow move one bit to the right end end

always @(*)begin if(expA > expB)begin expB = expB + n; end else if(expA < expB)begin expA = expA + n; end end always@(*)begin result_exp = expA + expB; end

always @(*)begin if((sigA == 1'b0) && (sigB == 1'b0))begin result_sig = result_sig + 1'b0; end else if ((sigA == 1'b1) && (sigB == 1'b1))begin result_sig = result_sig + 1'b1; end else if (expA > expB)begin result_sig = sigA; end else if (expA < expB)begin result_sig = sigB; end else if (manA > manB)begin result_sig = sigA; end else if (manA < manB)begin result_sig = sigB; end end always @(*)begin addition_of_a_and_b = {result_sig,result_exp,result_man}; end endmodule -------------------------------THE CODE------------------------------ -------------------------------THE ERRORS------------------------------ Error (10028): Can't resolve multiple constant drivers for net "result_man[23]" at math_adder.v(39) Error (10029): Constant driver at math_adder.v(43) Error (10028): Can't resolve multiple constant drivers for net "result_man[22]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[21]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[20]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[19]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[18]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[17]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[16]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[15]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[14]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[13]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[12]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[11]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[10]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[9]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[8]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[7]" at math_adder.v(39) Error (10028): Can't resolve multiple constant drivers for net "result_man[6]" at math_adder.v(39) Error (12153): Can't elaborate top-level user hierarchy -------------------------------THE ERRORS------------------------------