iCMOS amplifier two stage Objective: The objective of this project is to design, build, simulate, and write a technical report on directly coupled two-stage amplifier. The amplifier should have a common source voltage gain stage and common collector current gain stage. The two stages are connected in cascade where a single transistor (n-MOS) is the input that provide high input impedance. The second stage is a single BJT transistor amplifier with low output impedance. The stages match impedances (k2) to maximize power transfer. The common-collector (Emitter follower) stage can drive low impedance load Note: Atotal 4,1 * Av2 total Ail WithPeut 1 ITn 1. A, 2 10 v/v 2. Fi-100 300 Hz 3. FH 50 150 kHz 4. Rt>5 k210 kn 5. Vo-peak-peak = 3.0 V/V 6. Vdc = 5 V 7. Use any available BJT, NMOS transistors 8. Build using Q2N3904 and Q2N2906 Bipolar Junction Transistors or any other available ones and CD4007UBE NMOS iCMOS amplifier two stage Objective: The objective of this project is to design, build, simulate, and write a technical report on directly coupled two-stage amplifier. The amplifier should have a common source voltage gain stage and common collector current gain stage. The two stages are connected in cascade where a single transistor (n-MOS) is the input that provide high input impedance. The second stage is a single BJT transistor amplifier with low output impedance. The stages match impedances (k2) to maximize power transfer. The common-collector (Emitter follower) stage can drive low impedance load Note: Atotal 4,1 * Av2 total Ail WithPeut 1 ITn 1. A, 2 10 v/v 2. Fi-100 300 Hz 3. FH 50 150 kHz 4. Rt>5 k210 kn 5. Vo-peak-peak = 3.0 V/V 6. Vdc = 5 V 7. Use any available BJT, NMOS transistors 8. Build using Q2N3904 and Q2N2906 Bipolar Junction Transistors or any other available ones and CD4007UBE NMOS