Identify the type of register in which data is entered all a time and the output data is available one bit at a time Select one: O a. Parallel in serial out O b. Parallel in Parallel out O c. Serial in serial out O d. Serial in Parallel out Identify the correct statement for a Gated or control enabled D Latch Select one: O a Output Q follows the input D when the enable is LOW O b. None of the above O c. Output Q follows the input D when the enable is HIGH O d. The output toggles if BOTH of the inputs is HIGH Determine the out of the given timing diagram for the periods indicated as 1,2,3,4 .Assume the previous value of Q to be 0 Clock S R 1 2 3 4 Q Select one: O a. 1,1,0,0 O b. 1,0,1,0 O c. 1,1,0,1 O d. 1,1,0,0 Determine the MIN term expansion of f(a,b,c,d) =a'(b'+ d) + acd' Select one: O a. f =M(0, 1,2,3,5, 7, 10, 14) O b.f=m(0, 1, 2, 3, 5, 7, 10, 14) O c. f=M(4, 6, 8, 9, 11, 12, 13, 15) O d. f=m(4, 6, 8, 9, 11, 12, 13, 15)